With the recent shift towards digital information processing, low power and high throughput have a certain degree of importance in many modern communication systems. Aside from the demand for increasingly high throughput, the growing trend toward portable and wearable devices oftentimes limits the maximum energy consumption while maintaining affordability. Increases in the throughput of a device are often accomplished through increasing accuracy of the devices. Sometimes increases in accuracy are accomplished by complex and expensive designs. In this context, the demand for increasing the throughput can be at odds with demands for affordability and minimization of power requirements.
Increased accuracy of communications devices can sometimes be realized by precisely controlling the characteristics of components in the devices, such as semiconductor and passive component characteristics. The control of such characteristics, however, can be expensive. Moreover, in certain applications the level of desired control may not be possible using conventional component construction methods. Thus, such conventional devices can be designed to compensate for the mismatched components. Also, some traditional methods of compensation have required additional power consumption and can reduce the throughput of the communications devices.
Numerous components can affect the operation of a communications device. For example, the functionality of a communications device can be adversely affected by non-idealities of various passive components including, resistive, capacitive and inductive components. Likewise, non-idealities of active components, such as comparators, amplifiers, and various other semiconductor components, lead to problems in the operation of a communications device.
A specific example of a communications-type component with such non-idealities is an analog-to-digital converter (ADC). The capabilities of an ADC often determine a significant portion of the power consumption and affect the throughput of a communications device. One way to minimize conversion energy is to employ an inherently simple and efficient ADC architecture, such as a successive-approximation register (SAR) ADC based on passive charge redistribution. A time interleaved array of such devices built in modern 90-nm technology can achieve high speed while consuming only a fraction of the energy used in competing architectures. However, due to the parallelism involved in a time-interleaved approach, it can be desirable to cancel mismatch between the individual conversion channels.
Even though this form of converter architecture is more than two decades old, several aspects make it attractive for implementation in current and future technologies. First, due to their inherently simple structure and minimal analog complexity, SAR ADCs are known to exhibit excellent power efficiency. Secondly, their performance is expected to scale well with feature size reduction and tends to be fairly insensitive to the otherwise detrimental impact of supply voltage reduction and decreasing intrinsic device gain in deep sub-micron CMOS.
Despite these advantages, SAR ADCs come with a significant penalty in conversion speed. Since the digital output is resolved sequentially, the achievable conversion speed is fairly low causing potential problems with many wireless systems. For example, a wireless communication device implementing orthogonal-frequency-division multiplexing (OFDM) based ultra wideband (UWB) system may require ADCs with 6-bit resolution and throughput rates of approximately 500 MS/s. These performance requirements are hard to meet using a generic SAR ADC.
Time interleaving is a known method for increasing throughput in an ADC, SAR or otherwise. A time-interleaved array employs several ADCs that process the incoming signal sequentially. Ideally, the overall throughput of a time-interleaved ADC increases linearly with the number of interleaved channels, and the bit-resolution of the array is equal to the bit-resolution of the individual sub-ADCs. In practice, however, time interleaving can cause severe performance degradation due to mismatches between individual channels. Typically, at least three types of mismatches are considered: mismatch in gain, offset and timing. In addition, the nonlinearity of each channel and mismatch thereof can be an issue.
Offset mismatch between the different ADC channels, mostly due to random comparator offset, can also be an issue in such design. Assuming a basic differential pair input structure in the comparator, the offset is mainly determined by threshold mismatches in the input pair, where the standard deviation of threshold mismatch is inversely proportional to the square root of transistor area.
This issue can be addressed to some extent by increasing the device area. However, to reduce the offset by 10 times in a given environment, a one hundred-fold increase in area would be necessary. Assuming constant current density and minimum channel length to preserve speed, this would also correspond to a 100-times increase in comparator power dissipation. Another option is to employ analog auto-zero and offset cancellation techniques. While such schemes may have been attempted, they usually require additional timing overhead and sufficient device gain, which also translates into a power penalty for a given target performance.
Similar issues exist for other ADC configurations as well as other digital and analog circuits and their components. These and other characteristics present challenges to the implementation of communication arrangements, such as wireless communications arrangements.